Job Details:
Job Description:
Drives end to end development for substrate design from concept through tapeout and implements physical layout and routing of high volume product package design. Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs. Works closely with silicon and hardware teams to optimize silicon package board performance and pinout. Defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves DRCs to optimize package design. Completes documentation and collateral into the product lifecycle management system of record.
Qualifications:
Minimum Qualifications
-- Minimum of a Bachelor of Science degree in an Electrical, Computer, Mechanical, Chemical Engineering field or physics.
-- 3+years of prior experience/exposure with physical design (Package/PCB).
-- 3 +years of experience with Design Tool Suites (Cadence Siemens Mentor Graphics Expedition) Software and other Package related SW suites.
Additional Preferred Qualifications:
-- Experience with high-speed layout techniques that involved parallel and serial differential interfaces
-- Experience in Package/Substrate technology development
-- Ability to use Windows based office Suite (MS Excel, MS Powerpoint, MS Word etc)
-- Exposure to process driven execution track record would be preferred.
-- Strong communication and team player mentality.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, California, Santa ClaraAdditional Locations:
US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:
The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/ABenefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$89,620.00-$143,200.00Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.More Information
Application Details
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Organization Details
100 Intel Corporation
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