Job Details:

Job Description: 

Do Something Wonderful! 

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people’s digital lives. Come join us and do something wonderful!

Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver Mixed Signal solutions for products that impact customers lives? If so, come join us to do something wonderful. CEG (Client Engineering Group) designs and delivers the full range of client compute solutions on leading edge processes. The memory interface team within CEG develops cutting-edge high-speed memory interface designs such as LPDDR* and DDR* for use in Intel's latest microprocessors. We own the design from architecture definition to tape-out and Post Silicon support covering all aspects of a Mixed Signal design from Analog circuit to RTL development and structural implementation.

You will be responsible for, but not limited to:

We are looking for a versatile engineer who is familiar with both analog circuit design and RTL coding. This individual will be responsible for understanding circuit architecture documentation and translating architectural intent into behavioral model in System Verilog for analog circuits. The individual will then integrate and turn in the behavioral model into the PHY RTL repo and resolve logic simulation failures. The individual will also work with analog circuit designers who translated architecture intent into schematics, and confirm the behavioral model and schematics are functionally equivalent.

Experience in designing, developing, and building analog circuits in advanced process nodes for analog and mixed-signal IP’s will be helpful.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

BS degree + 1 years’ experience minimum, or MS degree

Preferred Qualifications:

• Transistor-level design experience
• Logic design experience
• HDL coding and verification experience, particularly with SystemVerilog
• Proven track record on design of high-speed analog and mixed-signal circuits.
• Understanding of architecture and integration aspects of DDR PHYs.
• Familiarity of LPDDR/DDR JEDEC specifications and related DDR Protocols.
• Understanding of design for yield and exposure to production challenges in latest technology process node.
• Experience with industry standard tools for Analog design such as Cadence ADE, Spectre, AMS verification, FEV, StarRC etc.
• Experience with Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training MRC and HAS/MAS specification documentation.

 

          

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Folsom

Additional Locations:

US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro

Business group:

The Client Engineering group (CEG) is a worldwide organization focused on the development and integration of SOCs, and critical IPs that power Intel's leadership products, driving the Client roadmap for CCG, and invest in future disruptive technologies.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$88,320.00-$132,660.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.