Job Details:

Job Description: 

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

Life at Intel

Diversity at Intel
 

As a Physical Design Engineer your responsibilities include but not limited to:

• Execute on Fusion Compiler synthesis flow, Auto Place and Route, Timing Performance validation, and Reliability validation which includes Layout Verification and DRC convergence, IP Integration Flows

• Partner with the DA team on innovation and initiatives to enhance existing automation, tools, and methodology.

• Identify and analyze problems, plans, tasks, and solutions

• Perform in a dynamic and challenging environment with drive and creativity

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must have a bachelor's degree in electrical engineering, computer engineering, computer science, or any STEM related field with 4+ years of experience - OR - master's degree in electrical engineering, computer engineering, computer science, or any STEM related field with 3+ years of experience in two or more of the following:
Synopsys or Cadence design (RTL to GDS) tools.
Synopsys-Primetime.
ICV or Calibre DRC/LVS Layout cleanup

Preferred Qualifications:
Experience with STA at both partition and SOC level
Synopsys design (RTL to GDS) construction and signed off tools.
Strong analytical ability, problem solving and communication skills.
Ability to work independently and at various levels of abstraction.
Experience in Perl, TCL/Tk programming.
Experience with TFM (Tools, Flows, Methodology) Development

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Arizona, Phoenix

Additional Locations:

US, California, Folsom, US, California, Santa Clara, US, Oregon, Hillsboro

Business group:

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$102,120.00-$169,020.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.