Job Details:

Job Description: 

Intel FPGAs offer a wide variety of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and built-in intellectual property (IP). All these combined with outstanding software tools lower FPGA development time, power, and cost for enabling product differentiation. Differentiation of your product from others is the difference from survival to prosperity.
Configurable FPGAs will require multiple design verification configurations that tend to increase the verification cycles. Thus, the need for a common test environment across many IPs of both HW and SW is the necessary verification cycle optimization as part of the shift-left strategy.
As the PCIe IP subsystem design verification architect, you get to define and implement the common test environment by working with the stakeholders from both HW and SW domains. You review the design requirements and develop the verification strategy for the subsystem. You do create test plans for RTL verification, define and execute subsystem simulation models, and find and implement corrective measures for test failures. You also analyze and use test results to improve test bench, and make use of various verification tools such as Scoreboards, Checkers, Generators, Bus Functional Models, etc.
In this position you will work closely with design architects and micro-architects, as well as design teams in determining the proper verification strategy for new design, defining, and providing feedback on test plans, developing and implementing white box coverage plans, participating and reviewing verification codes for efficiency and coverage, and driving any paradigm shifts needed in verification execution.

Qualifications:

Minimum Qualifications

• Bachelor of Science degree or Master of Science degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science (with FPGA design focus).
• At least 15 years of experience in designing or verifying FPGAs, SoCs or IP blocks.
• In depth knowledge of RTL language such as System Verilog or Verilog.
• In depth knowledge of industry standard tools and methods such as Synopsys VCS, Mentor/Siemens Questasim, Cadence Xcelium, OVM/UVM and UPF.

Preferred Qualifications

• Knowledge of PCIe protocols and usage models.
• Knowledge of object-oriented programming in TCL, Java, Python, or some other languages.
• Behavioral traits including but not limited to strong communication skills (written and verbal), tolerance of ambiguity, problem solving, teamwork, attention to detail, commitment to task, and quality focus.
• Experience with FPGA SW development platform especially on Intel® Quartus Pro.
• Experience in system interconnect bus such as AXI, AHB, AVMM, etc.
• Knowledge in Agile development and familiar with Scrum process.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.