Job Details:

Job Description: 

An SoC Design for Debug (DFD) Architect is responsible for coming up with the overall DFD architecture for SoC based on DFD requirements from customer, SoC design architecture, needs of post-Si Validation teams and IP teams. Should have hands on experience and be well versed in DFD feature implementation, validation, pattern delivery to post-Si teams and tools that are used for debugging SoC Designs in a Post-Si environment. Should be able to guide a team of junior-mid level experience Engineers for DFD feature implementation, validation (pre and post Silicon) and pattern delivery to relevant stake holders. Candidate should have overall experience of 15+ years with a minimum 10+ years of hands-on experience in the domain of DFD architecture, implementation and validation Hands on exposure on most of the below skills is preferred � ARM SoC based debug infrastructure including Core sight infrastructure (implementation and/or validation) � Exposure on SoC Cross Trigger Matrix including - Interface with CPU CTI channels and support from triggers to/from external PINS � JTAG based debug architecture (conforming to 1149.7 and 1687 based iJTAG standard) � ICL extraction and verification � Creation of test sequences in PDL format and debugging � Hands on experience of IP and SoC level VISA flow implementation and validation (including VRC and DVP integration) � Boundary scan insertion, pattern generation and simulation � Strong understanding of debug tools needed in post-silicon environment � SCAN Freeze and Dump and Array Freeze and Dump � Debug scheme for viewing internal SoC digital/analog static/quasi static signals on digital/analog view pins and/or GPIOs � Good understanding of APB/AHB/AXI/CHI interfaces � Process and voltage droop monitoring scheme within SoC using fublets � DFT mode STA constraints generation and validation for Design of Debug mode � Scripting expertise in PERL/python/TCL � Object oriented programming � Familiarity with GNU MAKE

Qualifications:

Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Master of Science degree in Electronics/VLSI Design Engineering with 13+ yrs of relevant experience, OR Bachelor of Science degree in Electronics Engineering with 15+ yrs of relevant experience Knowledge of digital electronics, logic design, and design for debug concepts. Good understanding of CPU Architecture. Understanding of a subsystem HW/SW stack, including the silicon, onboard HW components and connectors and debug interfaces such as JTAG, I2C, and UART. Experience developing post-silicon test/debug tools using C/C++ and/or Python. Experience with hands-on debug in post-silicon environment using debug tools such as using ITP/JTAG, Logic Analyzers and Oscilloscopes. Excellent problem-solving and interpersonal skills, as well as good written and verbal communication skills. Ability to work cross-geo/site when needed to accomplish results. Preferred qualifications: Knowledge of ARM, RISC-V and x86 ISA Prior experience with Intel products or other CPU/SoC products in a post-silicon engineering environment Experience developing debug methods and debug tools for SoC validation. Understanding of a subsystem HW/SW stack, including the silicon, onboard HW components and connectors and devices, BIOS, drivers, and applications is a plus

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.