Job Details:

Job Description: 

• We are looking forward to candidates with:
  In this position you will be responsible for Performance Verification (PV)/STA including timing analysis, noise glitch analysis for leading-edge designs.
  Development and validation of constraints for blocks, subFC and Full Chip
  Understanding of IO/ACIO timing closure
  Understanding of Synthesis , DFT insertions that include MBIST and SCAN.
  Timing execution and signoff convergence for func and test modes
  PTECO/Tweaker ECO flow and timing convergence
  Work closely with process technology team to understand process characteristics and set appropriate constraints in timing analysis flows and methodology.
  Interact with SoC customers to understand IP/SoC interface design requirements/objectives and develop appropriate interface signoff constraints for IPs.
  Mentor junior design engineers to build resiliency.

Qualifications:

• Qualifications

              Experience : Should have 10+ years of experience in relevant field
              Bachelor Degree in Electrical and Electronics Engineering or Master Degree in Electrical and Electronics Engineering or Computer Engineering

              Must have led at least 2 SOCs in capacity of SOC Sign-off lead especially. Solid Expertise in Primetime or Similar timing tools
          Good understanding of overall ASIC Architecture, Physical Design/DFT, Tools and implication on Timing Convergence
          Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA
          Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well.
          Teamwork / flexibility / ability to thrive in a dynamic environment are very important

              Strong Communications skills and the ability to effectively work with cross functional teams.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.