Job Details:

Job Description: 

DEG/IMSG seeks an experienced pre-Si verification engineer for its PCIe IP development organization, a dynamic team with a history of outstanding execution and industry-leading accomplishments. We are looking for an enthusiastic individual with a strong background in all aspects of IP development and a proven capacity for understanding new technologies, to help deliver on our charter as Intel's center of innovation for IO and Accelerator technologies.You will be responsible for, but not limited to:o Working with a high performing team to deliver fully functional IP's on Intel's latest process technology to reduce product risk for various enterprise IPs including PCI express and acceleratorso Interfacing with architects and senior design team members to develop test plans covering formal test environments, checker and coverage strategies.o Working on multiple tasks o Concept to design verification closure on complex blocks

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Candidate should possess a Bachelor's degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 7+ years' experience -OR - a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 5+ years experience -OR- PhD degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 3+ years experience ino Strong hands-on System Verilog Assertion coding experience and Formal verification environment development is required.o Experience working on verifying any Serial IP or Interface protocols (PCIe, CXL, AMBA)o Candidate should possess work experience in different Formal Verification Methodologies such as but not limited to Property Verification, C vs RTL Equivalence Checking, Sequential (RTL-RTL) Equivalence checking, etc. and in Formal Verification Techniques such as blackboxing, abstractions, assume-guarantee, etc.o Exposure to cadence Jasper tool with apps like FPV, UNR, COV, CSR, C2RTL desirable.o Design Verification experience verifying complex designs and leading projects from concept to verification closure.o Analytical and problem-solving skills.o Solid verbal/written communication skills.o Effective team player with continuous learning mindset.o Be willing to balance multiple tasks.o Prior experience in IP development teams would be an added advantage.o The candidate must be able to work independently and be self-motivated to identify, innovate upon, architect and deploy Formal Verification solutions.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.