Job Details:

Job Description: 

Develops custom layout design of analog blocks, complex digital, mixed-signal blocks, standard cell libraries, or memory compilers (e.g., bit cells, SRAMs, Register Files). Performs detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding. Conducts complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks. Uses custom autorouters and custom placers to efficiently construct layout. Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests. Develops and drives new and innovative layout methods to improve productivity and quality. Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.

Qualifications:

MS/ME/MTech in VLSI or BS/BE/BTech in Electronics Engineering with a minimum of three years of industry experience in designing and optimizing VLSI layout at the cell and or block level on different silicon process technologies is required. Additional Desired Qualifications Knowledge of CAD layout tools eg Cadence Virtuoso Synopsys Custom Compiler any other industry-standard layout development tool Experience using design rule checkers and layout verification tools Knowledge of additional layout automation capabilities eg process shift Knowledge of scripting languages TCL Perl Skill Python for design automation is a plus

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.