Job Details:

Job Description: 

Architect, design, develop, and validate power management pCode for IPs and SoCs. Develops and implements power management features and algorithms to manage the SoC and platform with clear partitioning on firmware and hardware. Collaborates on silicon architecture definition and develops the power management microarchitecture specification, presilicon verification test plans, and performs functional verifications as per specifications. Develop IP Unit models and definition of verification infrastructure and related TFMs needed for power management verification. Conducts power and performance analysis and optimization to meet postsilicon performance goals until product PRQ/PRT, working in collaboration with PnP teams. Provide recommendations for future power management architectures. Influence hardware, OS, and platform designs to meet the power performance criteria. Develops methodologies and models to drive continuous improvements in developing and validating power management flows, features, and algorithms. May also research and adopt machine learning and other AI applications to improve performance and user experience.

Qualifications:

o Prior Experience in SoC development / Embedded systems is mandatory. o Minimum 4 years of experience in SoC/Embedded Systems with at least 1 year of firmware/software validation experience dealing with hardware level intricacies o Proficient in Assembly programming/C/C++ and in a microcontroller environment (Tensilica/ARC/ARM Cortex M or similar)o Exposure to CPU, Graphics, Media, Display, DDR, Imaging, Audio, IO systems is highly desired with strong expertise in any of these domains o Knowledge of one or more power management features and functionality, including: power states/flows, power consumption, power delivery, reset sequence, OS power management, device power management and stability between power management subsystem/domains and other subsystems in the system setting o SW/HW Validation experience: unit / functional/ integration / exploratory o Debugging techniques local/remote, including profilers, debuggers, and system monitoring hardware desired o Ability to learn new skills quickly and independently o Excellent written and verbal communication skills

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.