About our Organization: 

As part of the Core Engineering Group, we develop Intel's main and most valuable and complex IP - the CORE. The CORE is the central part of many of Intel's products, such as: Desktops, Notebooks, Servers, Cloud CPUs and more. Our CORE is in the heart of hundreds of millions of products being sold every year, and is driving the internet, networking industry, cloud compute, communications, consumers and more. 
 
About the Team:  
The P-Core DFT Team owns the architectural definition, logic design and verification of the DFT infrastructure, features and flows in the P-Core. 
Our mission is to drive qualitative and timely DFT deployment on P-Core projects while ensuring high coverage to reduce DPM (Defects Per Million) and efficient HVM (High Volume Manufacturing) testing mechanisms to support TTR (Test Time Reduction), as well as define future DFT methodology. 
We work jointly with all the functional design and verification engineers in the P-Core, and collaborate closely with the post-silicon product engineers, as well as the SoC engineers of the products which consume P-Core. 
We are a newly formed team with a growing scope and plenty of room to grow, while ensuring great technical mentorship by experts in the DFT field. 
DFT is a fascinating arena which involves all aspects of design and process technology and offers a unique opportunity to be a key part throughout a project's life cycle. 
 
About the Job:  
In this role, you will be responsible for the design, code, simulate and integrate DFT blocks (including TAP, SCAN, MBIST, etc.) into functional logic and ensure their high-quality integration. You will also participate in the definition of CPU architecture and microarchitecture features to make sure they are covered by DFT. 
In addition, you will provide DFT timing closure support as well as test content generation and delivery to manufacturing for various DFT content. As well as developing HVM (High Volume Manufacturing) content for rapid bring up and ramp to production on the automatic test equipment (ATE).  
As part of this job you will apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. You will also ensure DFT design features are verified correctly and resolve and implement corrective measures for failing RTL tests to assure features quality. 
In addition, you will be responsible for optimizing logic to qualify the design to meet power, performance, area, timing, test-coverage, DPM, and test-time goals and physical design integrity. You will also collaborate with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and apply learnings on future products.