Job Details:

Job Description: 

IFS Foundry Technology Engineering and Customer (FTEC) team is a critical team to lead Intel's design methodology and flow in advanced technology. As a role in IFS FTEC team, should be familiar with entire ASIC (APR) design flow and qualified to have design experience in ASIC (APR) design. In this position, the candidate will be responsible for the ASIC (APR) design methodology/flow development especially in the areas of synthesis, floorplan, PnR, Timing, 3DIC, ECO, Layout Verification and PG/EMIR design. As part of this role, the candidate is expected to work with various cross functional teams and external EDAs to oversee the execution all the way. The candidate is responsible to run PPA benchmarking, validate new design flow/methodology, and figure out the potential flow issues. In addition to the above, the candidate's ability to come up with a design solution is a plus.

Candidate applying for the ASIC Design Methodology and Flow Development Engineer position shall have expertise in any or multiple areas listed below:

1) Advanced ASIC (APR or PD) design including Synthesis, Floorplan, PnR, PG/EMIR, Timing, Layout verification and ECO

2) ASIC (APR) design flow development and EDA tool certification;

3) EDA design tool and design automation Self-motivated and detail-oriented, capable of articulating complex concepts and solutions ;

4) EDA views development and qualification;

5) Qualification of PDK/reference flows/Foundation IP.

6) 3DIC implementation

The ideal candidate should exhibit the behavioral traits such as: Collaboration mindset with a focus on development/design methodology, operate seamless in cross functional or matrix organization setup, and deftly handle internal & external EDA/ecosystem engagements.

Qualifications:

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
MS/Ph.D. degree in Electrical Engineering, Computer Science, or a STEM related field of study
5+ years experiences in ASIC (APR) design, flow development, and EDA enablement; and/or
Technical background in EDA tools
Programming skill: TCL, PERL or SKILL

Preferred qualifications:
Experience in PDK development and enablement is a plus.

Experience in tools, flow & methodology development in FinFET technologies

Experience in handling EDA & PDK development stake holders

Experience in EDA feature development and support in Physical design & signoff domains

Experience in latest 3DIC implementation and/or methodologies

Good communication and presentation skills to executive project coordination

Experience in AI/ML deployment in physical design

Programming skill: Python

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence.