Job Details:

Job Description: 

Join FIP for Analog IP team and QA Engineer Manager/team lead. Duties include(but not limited to): Responsible leading a team to perform all aspects of Analog and Digital design this includes PLL, TVSENSE, Crystal Oscillator for high quality and best PPA with solid understanding of chip level. Make sure IPs meet all QA checking, review and editing documentation and work with customers, release team, PDK team. Create project methodology/or flow developments. Responsibilities include large-scale block layout, complex layout blocks, small to medium scope section lead, small to medium scope layout projects with mentorship and guidance, development or improvement projects, tool evaluations, etc. � Lead, coordinate, facilitate and monitor the daily activities of a small to large group of support resources within their section or project team while holding a leadership role. � Able to contribute to design of the analog IPs. � Prioritizes workload to successfully manage multiple tasks and responsibilities concurrently. � Manages daily operations within their assignments, showing appropriate consideration for established project objectives and standard project methodologies. � Develops detailed task lists, forecasts resource requirements, and creates long range schedules for sections and small projects. � Frequently involved in developing the skills of less experienced designers through formal training, coaching or mentoring. � Proactively addresses and communicates issues impacting productivity and works to resolve those roadblocks. � Creates bottoms up elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, IOs/ IP level floor plans, abstract view generation, RC extraction and schematic. � Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. � Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. � Requires expansive knowledge and practical application of methodologies and complex IP design. � Typically performs as a highly proficient technical individual contributor or specialist on complex design and leadership assignments. � Expert IOs900 and QA methods. � Customer support.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications:- Candidate must possess a BS degree with 6+ years of experience or MS degree with 4+ years of experience or PhD degree with 2+ years of experience in Electrical or Computer Engineering or a related field. 5+ years' experience with: Analog IPs and mixed signal environment, familiar with reliability (including ESD), IR, EMIR, Lifetime simulation tool to support different applications and market target. Preferred Qualifications: 5+ years of management experience along with QA experience.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.