Job Details:

Job Description: 

We are looking for a highly motivated SoC Design Verification Engineer with technical and leadership skills. In this role, responsibilities include: Functional logic verification of SoC to ensure design will meet specifications Define and develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications Execute verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs Replicate, root cause, and debug issues in the pre-silicon environment. Find and implement corrective measures to resolve failing tests. Collaborate and communicate with SoC architects, microarchitects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Document test plans and drive technical reviews of plans and proofs with design and architecture teams. Incorporate and execute security activities within test plans, including regression and debug tests, to ensure security coverage. Maintain and improve existing functional verification infrastructure and methodology. Absorb learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate must possess a BS degree with 8+ years of experience or MS degree with 6+ years of experience or PhD degree with 4+ years of experience in Electrical/Computer Engineering, Computer Science or related field . Highly experienced in SoC/IP/Subsystem Verification (UVM, System Verilog) Good knowledge of bus protocols such as AXI and high speed serial link IP such as PCIe Hands on experience with RISC-V based Validation with C language. Hands on experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE Test writing, Regression management, Coverage (Functional/Code) Excellent problem-solving skills, Strong communication and collaboration skills. Preferred Qualifications: Write verification strategy/plan, test plan, bug filing (Jira/HSD) Deep knowledge of JTAG and serial protocols such as UART SV/UVM Testbench creation, VIP/BFM integration and configuration. Good scripting knowledge using Perl/Python Front end design and verification environment setup and maintenance

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

India, Hyderabad

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.