Job Details:

Job Description: 

In this position, your responsibilities may include, but not be limited to:
� Working on static timing analysis setup and signoff of multi-corner multi-voltage designs. Areas of focus include timing analysis, power estimation, extraction and noise glitch analysis across internal and external foundry processes
� Owning timing execution to meet timing requirements including timing budgeting, repeater planning, automatic constraints/exceptions generation and management, and other key differentiating capabilities for quality and efficient timing closure
� Hierarchical timing analysis and convergence at block, section and fullchip level.
� Engaging closely with Design teams to understand the design and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations.
�  Understanding CTS strategies, LVF/POCV variations and providing feedback to the implementation/methodology teams.

The ideal candidate should exhibit behavioral traits that indicate:
� Self-motivator with strong problem-solving skills
� Strong leadership skills with ability to mentor junior designers
� Excellent interpersonal skills, including written and verbal communication
� Ability to work as part of a team and collaborate in a high-paced atmosphere
� Ability to provide technical direction to the team and influence project execution and methodology

Qualifications:

• Qualifications

� Mtech/Btech Engineering Degree in field of Electrical, Electronics, Computer Science with 8+/10+ yrs of relevant RTL2GDS experience
� Demonstrated ability in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must.
� Expertise in industry standard EDA tools (Primetime, Tempus) and ASIC design flow is required
� Multi-voltage scenarios design handling knowledge is expected. STA closure/convergence execution on Low power designs is an added advantage
� Proficiency in scripting language, such as, Perl and Tcl.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

India, Hyderabad

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to continue to advance PC experiences to deliver the real-world performance people demand. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.