Senior Formal Verification Engineer, Annapurna Labs - Haifa | Amazon Job

Job Description

Annapurna Labs, a division of Amazon Web Services (AWS), develops innovative hardware and software for AWS cloud infrastructure, including AWS Graviton processors and the AWS Nitro System.

Working for Annapurna Labs is thrilling, fast-paced, and a constant learning experience.

Formal verification is everywhere in our projects. Each project has hundreds of formal environments. They range from small blocks with sophisticated data crunching or complex FSMs up to large systems, including chip-fabric deadlock verification.

The Role:
As an L6 Formal Verification Engineer, you'll be the official technical lead and own the FV strategy for a specific subsystem across Graviton and Nitro. You'll distribute work, review from strategy through sign-off, and mentor the engineers on your team. You'll also help shape the FV methodologies the whole team uses.

Your Ideas Shape the Team:
We constantly improve our methods, and any good idea can change how we verify. There are no limits on what formal verification can influence, or on how you can influence formal verification. Senior engineers on our team are co-inventors on formal verification technology patents.

Key job responsibilities
Own the formal verification strategy for a specific subsystem.
Lead a team of FV engineers technically, from work distribution and reviews through sign-off.
Mentor engineers and grow their formal expertise.
Drive and evolve team-wide formal methodologies.
Build and apply AI and agentic flows in formal verification.
Work closely with design teams to define verification intent and improve design quality.

A day in the life
What We Offer:
* Broad influence on almost every aspect of how the team works
* AI and agentic flows built into how we do formal verification
* A true engineering partnership with design, including joint patents
*The chance to apply formal to Graviton and Nitro, from complex blocks to full-fabric deadlock problems

Basic Qualifications:

- Bachelor's degree in Electrical Engineering, Computer Science, or a related field
- 8+ years of hands-on formal verification Expert knowledge of SystemVerilog Assertions (SVA)
- Hands-on expertise with industry formal tools (any vendor)
- Experience owning formal verification of complex designs through sign-off

Preferred Qualifications:

- Abstraction and complexity reduction techniques
- Cover-based and semi-formal verification, and helper assertions
- Protocol knowledge: AXI, CHI, networking
- Familiarity with AI/ML applications in verification

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