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Intel Foundry - Platform Enablement Engineer - USA - AZ - Chandler

1 day ago


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Job Opportunity Details

Type

Full Time

Salary

Not Telling

Work from home

No

Weekly Working Hours

Not Telling

Positions

Not Telling

Working Location

USA - AZ - Chandler, United States   [ View map ]

Job Details:

Job Description: 

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first Open System Foundry model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient, and sustainable source of supply.

We are looking for a Platform Enablement Engineer to join IFS Design Engineering Platform Office team, who has a detailed understanding of Hard IP collateral requirements as well as QA (Quality Assurance).

The candidate will work on assigned external/internal customers with their integration of Intel Design Kit (including but not limited to IPs) into their SoC and provide technical support.

Your specific responsibilities may include but are not limited to the following:

  • Work with cross-functional teams on collateral readiness, including IP integration into SoC activities.
  • Engage with IP development team to ensure all IP collaterals are generated and provided.
  • Engage in collateral QA for smooth usage of platform collaterals and integration of IP into SoC
  • Engage in the upfront identification and documentation of customer requirements, working with the collateral design teams to disposition requests.
  • Track collateral schedules/milestones/deliverables.
  • Drive resolution of customer issues related to the collateral generation, logic design verification, collateral release, and integration in the SoC environment.

The Platform Enablement Engineer (Open)will exhibit behavioral traits that demonstrate:

  • Excellent verbal and written communication and collaboration skills.
  • Strong communication and collaboration skills, including a willingness to work with others, and the ability to tolerate ambiguity and highly complex decision environments.
  • Enjoy debugging and problem-solving in a team environment.
  • Able to work independently with the design team and customers to solve remotely.

Qualifications:

What we need to see (Minimum Qualifications):
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

  • Bachelor's degree in Electrical Engineering, Computer Engineering or similar discipline with 4+ years of experience or Master's degree in Electrical Engineering, Computer Engineering or similar discipline with 3+ years of experience.
  • 2+ years of experience in any or all of the following: partitioning, synthesis, floorplan, IO designs, clock tree, and timing closure for ASICs.

How to Stand out (Preferred Qualifications):
 

  • Experience RTL design using Verilog/System Verilog.
  • Experience with VCS, Verdi, Spyglass, or equivalent tools.
  • Experience with crossfire or other QA tools, understand Industry standard tools.
  • Experience with digital flow for RTL2GDS development.
  • Experience in chip-level/subsystem integration.
  • Experience with IP development and product lifecycle (Gladius milestones for HIP)
  • Experience with at least one or more industry-standard IO interfaces, including DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc.
  • Proficient in scripting languages like Perl/Tcl/Python and power-aware RTL and UPF flow is a plus.
  • Good understanding of IP integration and design flow challenges within the context of subsystems and SOCs.

Amazing Benefits!

Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel’s benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment.  Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Arizona, Phoenix

Additional Locations:

US, California, Folsom, US, California, Santa Clara, US, Oregon, Hillsboro

Business group:

Intel Foundry is dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. As stewards of Moore's Law, we innovate and foster collaboration within an extensive partner ecosystem to advance technologies and enable our customers to design leadership products. Our strategic investments in geographically diverse manufacturing capacities bolster the resilience of the semiconductor supply chain. Leveraging our technological prowess, expansive manufacturing scale, and a more sustainable supply chain, Intel Foundry empowers the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, a customer-oriented service organization that is dedicated to the success of its customers with full P&L responsibilities. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html


Annual Salary Range for jobs which could be performed in

US, California:$105,797.00-$175,105.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.


More Information

Application Details

  • Organization Details
    755 Intel Microelectronics (M) Sdn. Bhd.
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