Job Details:

Job Description: 

Come and join a winning team at Intel. As a Formal Verification Engineer, you will be responsible the following but not limited to:

• Verify microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs (Server IPs, Graphics, processors and SOCs).

• Use the hardware architecture design and RTL implementation details.

• Define the Formal Verification scope, deploy the right strategy to prove the correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design.

• Carve out the right boundaries for the design, create comprehensive formal verification test plans, track, verify, apply abstraction techniques, and converge on complex designs to deliver a high-quality design on schedule and articulate the ROI. Analyses new methodologies, evaluates new tools and corroborate results.

• Work with vendors on resolving hard design and tool problems.

The ideal candidate should exhibit the following:

• Excellent problem-solving and debugging skills.

• Effective communication and teamwork skills.

Qualifications:

Minimum qualifications are required to be initially considered for this position.

Minimum Qualifications:

• Bachelor's degree in electrical engineering, computer science or a related field with 4+ years of experience or Master's Degree with 3+ years of experience in related field or PHD Degree with 1+ years of experience in related field.

• 2+ years of experience digital design principles

• 2+ years of experience with hardware description languages (Verilog, VHDL)

• 1+ years of experience in formal verification methodologies and tools. (e.g., Synopsys VCF, Cadence JasperGold, etc.).

• 1+ years of experience with formal verification languages (e.g. SystemVerilog Assertions, PSL).

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Santa Clara

Additional Locations:

US, California, Folsom, US, Oregon, Hillsboro

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$116,602.00-$192,374.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.