Job Details:

Job Description: 

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Defines, builds, and evaluates standard cell layout to meet design requirements such as power, performance, area, and cost. Develops standard cell layout libraries and drives transistor-level circuit design and performance analysis. Works with IP and SoC design teams to understand physical requirements and integrate ideas to meet performance, power, and area goals. Works with process technology teams to define and refine process requirements for standard cell design. Serves as the primary point of contact between design and standard cell library providers to ensure that design requirements are being met.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: � Bachelor's degree in electrical engineering, Electronics Engineering or related field and 3+ years of experience designing standard cell layouts in a relevant domain (e.g. digital design), or related work experience. � 3+ years of experience using layout design and verification tools (Cadence, Custom Compiler,LVS, DRC,QRC, layout quality checks). Preferred Qualifications: � Master's degree in electrical engineering, Electronics Engineering or related field and 3+ years of experience designing standard cell layouts in a relevant domain (digital design), or related work experience. The requirements listed would be obtained through industry-relevant job experience. We are looking for Standard cell Layout expertise in 14nm, 10nm, 7nm, 5nm, 4nm and 3nm. This position would allow to work in the cutting edge of semiconductor technology and be part of defining the technology. The Candidate will be responsible for the layout design of the standard cell, Power management, ECO and custom cell. Follow design guidelines set forth by the Engineering and Layout design leads in delivering high-quality deliverables promptly.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.