Job Details:

Job Description: 

In Q4 2023, Intel® announced Altera® will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel® . This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future.

As a FPGA Silicon Design Engineer, you will be responsible for, but not limited to, the following:

• Develop the system model, algorithm, and subsystems for integration in full chip designs.

• Participate in the definition of architecture and microarchitecture features of the block being designed.

• Create prototypes, simulate models, and specify systems requirements.

• Prepare and design logic diagrams and codes for implementing system design and test specifications.

• Deliver software models for device level bring up, including user visible functionality, timing, and power.

• Apply RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.

• Review the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Secondary responsibility will be to document final design specifications and features that can be used for customer consumption.

The ideal candidate will have the following skills in addition to the qualifications listed below:

• Excellent written and verbal communication skills.

• Deep knowledge of ASIC platforms and FPGA platforms.

• Knowledge of Verilog, System Verilog and System Verilog Assertions

• Experience with signal processing, algorithms investigation, modelling, and prototyping.

• Must have experience in hardware acceleration targeting FPGAs (automated and manually implemented)

• IP development (IO peripherals, DMAs, external memory controllers, etc…)

• Interconnects architecture definition (APB, AXI, Avalon, etc..)

• Embedded system design (HPS hardware and Nios II/V hardware + baremetal)

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements:

• Bachelor’s degree in electrical engineering, computer science, or related field.

• 9+ years of experience in system modeling or system design.

• 9+ years of experience with gathering requirements and creating design specification documents.

• 9+ years of experience in RTL design for ASIC and FPGA.

Additional Preferred Qualifications:

• Experience in Git or GitHub revision control system.

          

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, San Jose

Additional Locations:

US, Oregon, Hillsboro, US, Texas, Austin

Business group:

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$162,041.00-$259,425.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence.