Job Details:

Job Description: 

Creates methodologies, models, and flows for advanced design rules for a specific process node and characterizes those models through silicon validation. Ensures IP and SoC design meets requirements and standards for a specific manufacturing process technology. Identifies ways to optimize silicon designs by evaluating device performance over a range of operating conditions. Resolves prototype issues and determines whether problems are design or process related. Conducts experiments to identify potential challenges in the process and ensure that the process meets yield, quality, and reliability standards. Drives continuous improvements to enhance the designs, materials, and methodologies. Designs, validates, and characterizes analog building block devices and template cells. Disseminates process development information to design groups, ensures it meets future product requirements, and extracts necessary technical and device performance data for IP and SoC designs. Works with IP and SoC design teams to capture and optimize process requirements to enable competitive designs and products.

#DesignEnablement

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

- Candidate must possess a MS degree with 2+ years of experience or PhD degree with 1+ years of experience in Electrical, Computer Engineering, or related field.

Experience in the following:

- Experience in using Synopsys Fusion compiler, ICC2, DC or Cadence Innovus, Genus.

- IP/SoC physical design optimization and methodologies for optimal Performance, Power, Area and Cost (PPAC).
- Experience driving physical design EDA tools, design reference and sign-off flows in advanced process technologies, DTCO PPA and EDA vendor engagement.
- Low-power and multiple clock domain design.
- Scripting skills using a programming language such as Python, TCL, etc.

Preferred Qualifications:

Experience in the following:

- Transistor theory related to latest process technologies.
- Developing and maintaining design flows from synthesis to signoff.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Santa Clara

Additional Locations:

US, Arizona, Phoenix, US, Oregon, Hillsboro

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$123,419.00-$185,123.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.