Job Details:

Job Description: 

About the Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Foundry Technology Development (TD) is the heart and soul of Moore's Law at Intel. TD has enabled Intel to create world-changing technology that enriches the lives of every person on earth. TD's more than 10,000 employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. You will be a key member of the growing Design Enablement Application and Support team and will own significant customer enablement tasks in a fast-paced and technically challenging environment.

Job Description:

Design Automation engineer will develop and maintain complex infrastructure and automation for Integration QA of Foundational IP, consisting of Standard Cell Libraries, Memory Compilers, Custom Embedded Memories and AMS IP developed by RnD teams at Intel Foundry. This work is critical for ensuring that we can execute SoC design workflows across the breadth of the Intel Foundry EDA and IP offering. The solutions developed by Design Automation engineering team must be robust, scalable, easy to debug and generate reproducible results. Integration QA workflows will include significant design data analytics component.

The responsibilities will include:

Development of requirements, specifications and design automation solution architecture.
Manage development of QA workflows, including integration of EDA tools, workflow testing and release strategies.
Manager support of the internal Design Enablement teams executing integration QA, including debugging of issues in the workflow execution.
Guide KPI definition and implementation of data analytics solutions for QA execution results, regression vs. previous iterations, workflow bottlenecks.
Coach the team members in proactive identification and resolution of issues, work on continuous improvement of usability, runtime, storage optimization, and ways to improve test coverage.
Foster close collaboration with RnD and Application Engineering team on identifying and addressing gaps in QA.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with 6+ years of experience or MS degree with 4+ years of experience or PhD degree with 2+ years of experience in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering or a related STEM field.

• Managing Design Automation teams in one of the following domains: SoC Design or IP Design or FIP development and QA.

• Experience in one or more of the following EDA domains: Front End Design or DFT or Synthesis and Layout or RV or Sign Off.

• Hands on experience with one or more EDA tool stacks: Synopsys or Cadence or Siemens EDA.

• Software development skills: TCL and Python programming.

• Deep understanding of foundations of software architecture and design, testing and deployment methodologies.

Preferred Qualifications:

• Docker, VirtualBox, cross-platform application testing and deployment.

• Familiarity with project management best practices.

• Understanding of SoC and IP design and verification workflows.

• Jira Software platforms.

• Design and sign off on advanced process nodes, including statistical timing analysis, OCV.

• Understanding of IP QA and acceptance practices.

• Foundational IP domain.

• Cloud EDA.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$162,041.00-$259,425.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.