Job Details:

Job Description: 

We are the full chip SoC Integration team looking for Senior Layout Methodology and Integration development Engineer to work on Test Chip Lead Vehicles, which are primarily used by our Design Enablement (DE) and Logic Technology Development (LTD) team for Intel's next generation technology development and high-volume certifications. This role primarily focuses on the custom layout domain, full chip integration, tapeins and includes engagement with manufacturing partners on cutting-edge process nodes.

This role includes, but is not limited to, the following responsibilities:

- Developing Layout design methodology and productivity automation for cutting edge process nodes.
- Work on Testchip development using pre-production PDKs 0.01 or lower
- Building and executing tactical plans to converge hierarchical SoC layout designs against aggressive schedule requirements.
- Qualification of the full chip design to meet tape-out requirements.
- Working with tool/flow owners and vendors for ongoing tool/methodology improvement.
- Motivation to continuously learn and drive to push improved layout productivity and efficiency.

#DesignEnablement

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

- Candidate must possess a MS degree with 2+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering or Computer Engineering or related fields.

Experience in the following:

- Full chip SoC integration or IP Handoff.
- Established layout design experience on cutting edge technology nodes.
- Scripting or programming languages, such Perl or Python or TCL, etc.
- Expertise in Cadence Virtuoso layout suite or Custom Compiler or similar.

Preferred Qualifications:

Experience in the following:

- Industry standard physical design tools such as Cadence Virtuoso, Synopsys Fusion Compiler.
- Writing Synopsys ICV or Calibre rule decks.
- Proven Ability to provide automation support to improve layout productivity.
- Managing complex projects from definition to tapeout, managing schedule and identifying bottle necks for project execution.
- Working on projects that are designed on pre production PDKs.
- Power grid analysis and sign off using industry tools at SoC level.

- Expertise in understanding complex design rules on leading technology nodes.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.