Job Details:

Job Description: 

As an EDA Tools Software Engineer in the Test Chip Engineering group, you will be responsible for the development of runset and validation methodologies for Test Structure Design Rule Check to support design of Intel's next generation process technology and yield test chips. Your responsibilities will include, but not limited to: - Development of Design Rule Check (DRC) run-set software to implement test structure process design rules.- Validation and support of test chip layout design for the latest process nodes. - Collaborating with semiconductor process technologists to define test structure designs. - Develop the validation methods for e-test, yield, and defect metrology test structures.- Troubleshoot design and DRC, LVS, verification issues with complex physical design flows and tools. About the team and organization: Intel's Lead Vehicle Development (LVD) Team is one component of the larger Design Enablement (DE) organization, that provides design and manufacturing services to a variety of internal and external customers who leverage Intel's holistic design and manufacturing expertise to deliver unique circuits and systems at the leading edge of the technology curve. LVD's mission is to develop test-chips and other hardware prototypes that enable our customers to use Intel's most advanced process technologies to develop innovative products and reduce their time-to-market. Candidate must exhibit the following behavioral traits/skills:- Analytical and computer programming skills.- Be able to work in a team collaborative environment. This is an entry level position and compensation will be given accordingly.

#DesignEnablement

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Candidate must possess MS degree with 6+ months of experience or PhD degree with 1+ years of experience in Computer Engineering, Electrical Engineering, Computer Science, or other engineering fields.

Must have the required degree or expect the required degree by the date of start.

6+ months of experience in the following:

- Digital/Analog design or verification, physical verification, parasitic extraction, or electronic design software development/automation.
- Solid programming and scripting languages such as Python, Tcl, Perl or C++

Preferred Qualifications:

6+ months of experience in the following:

- Unix or Linux operating system.
- DRC/LVS runset development or support in any of following industry-standard EDA tools: Cadence Virtuoso, Synopsys ICV, Siemens Calibre
- DRC verification.

          

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.