Job Details:

Job Description: 

The Processor Subsystem Architect will be responsible for defining and architecting RISCV/ARM based processor subsystems for Intel FPGA products on state-of-the-art process nodes and will provide technical leadership to the rest of the team in all aspects related to the domain. The role covers understanding system requirements, converting those to specification/architecture and definition of processor subsystems that can scale to be seamlessly used in different products and/or bigger subsystems. The architect will be responsible for working with architects and engineers in various global teams in Intel such as FW/SW, DFT, DFD, security, SoC integration to ensure that the processor subsystem architecture meets requirements on all these fronts, with excellent PPA metrics.

Qualifications:

The successful candidate's minimum qualifications and responsibilities will include, but not limited to, the following:

• BS in Electrical Engineering or equivalent, with a minimum of 10 years of experience in VLSI design and architecture, on advanced process nodes
• Must have been part of entire silicon cycle from architecture to tapeout and successful silicon bring-up, at least for 1 product
• Must be very strong on digital design including clocking, resets, power, CDC, RDC.
• Must be able to architect HW accelerators and identify/analyze/meet PPA requirements
• Must have strong understanding of ARM/RISCV and subsystem components such as DMA, NoC/NIC, Interrupt controllers (GIC-600 etc), Debug/trace (SoC-600 etc), with 5+ years of experience on these.
• Must have in-depth understanding of AMBA protocols such as ACE, AXI, AHB, APB and interconnects
• Must have working knowledge of HW-FW interaction, HW+FW+SW partition and RTOS
• Must have working experience on DFT (scan, mbist), DFD (debug/trace), synthesis/STA
• Must be able to review microarchitecture, RTL, CDC/RDC/Lint reports, performance/timing/power reports and debug, resolve issues in execution very quickly.
• Low power design experience with UPF flows is a plus
• Experience with security algorithms, secure boot flows, access control with TrustZone/WorldGuard would be a plus
• Experience with functional safety (FuSa) and IP/SoC expertise with definition + implementation of FuSa would be a plus
• Experience on virtual platforms for early SW development enablement with models of processor, HW is a plus.
• Must have excellent analytical and communication skills
• Must be result-oriented and self-driven to learn, innovate and move things at a fast pace

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

India, Hyderabad

Business group:

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.