Job Details:

Job Description: 

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, come join us to do something wonderful.

Intel's Test chip group is looking for a Physical Design Engineer to contribute in the test chip integration domain working with IP partners. We are designing innovative solutions across multiple technologies and unique architectures that fuels Intel's servers, clients, and graphics microprocessors. You will collaborate with architects, logic designers, and analog engineers in evaluating implementation details of complex design features. You will perform all aspects of the SoC design flow from high-level design through synthesis, place and route, timing analysis and power reduction.

Your responsibilities may include but not be limited to:

• Family and/or block-level floor planning, Power supply and power grid planning and analysis, Logic synthesis of design blocks.

• Formal Equivalence Verification (FEV), Clocking network planning and analysis, Auto Place-and-Route (APR) using Synopsys ICC tools.

• Timing verification using Synopsys Prime Time, Physical verification - Layout vs. Schematic (LVS), Design Rule Checks (DRC), Electrical Rule Checks (ERC)

• Design for Manufacturability checks (DFM), Reliability Verification Debug and resolution of integration issues at parent level.

• Complete design reviews and design signoff flows and assist in the preparation of the full-chip layout design database for introduction to manufacturing.

 

In addition to the qualifications listed above the ideal candidate will also have:

• Excellent analytical and problem-solving skills.

• Strong verbal/written communication skills.

• Effective team player with continuous learning mindset.

• Willingness to balance multiple tasks.

• Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications:

• Candidate will be pursuing a Master's degree in Electrical Engineering or Computer Engineering.

Coursework in:

• SoC Design Flows: Experience with industry standard EDA tools (i.e. Synopsis, VLSI circuits, design techniques, and sub-micron CMOS technologies.

• Scripting skills using a programming language such as Perl, TCL, or Python.

Preferred Qualifications:

• Computer architecture and logic design fundamentals.

• Hardware description languages such as Verilog or System Verilog.

          

Job Type:

Student / Intern

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Arizona, Phoenix

Additional Locations:

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.