Senior ASIC Engineer - China, Shanghai | Nvidia Job

NVIDIA is seeking an ASIC Design Engineer to help develop advanced video IP for the world’s leading SoCs and GPUs. The NVIDIA MMPLEX Video team delivers video solutions across NVIDIA product lines, from consumer graphics and self-driving cars to the rapidly growing field of artificial intelligence. This position offers the opportunity to make a real impact in a multifaceted, technology-focused company, contributing to video codec designs from algorithm and architecture exploration through implementation and verification. You’ll join a globally distributed team of outstanding engineers working to push the frontiers of what is possible today and define the platform for the future of computing.

What you’ll be doing

• Explore video algorithms and architectures across quality, performance, power, and area.
• Define microarchitecture and implement verified HLS/RTL designs that meet PPA and timing goals.
• Set verification and quality gates to confirm changes are correct and ready for integration.
• Use AI where useful to speed ASIC work; validate outputs with engineering judgment.
• Collaborate with architecture, design, verification, SoC, emulation, and implementation teams.

What we need to see

• BS/MS in Electrical Engineering, Computer Engineering, or a related field.
• 3–5 years of ASIC design experience, contributing to chip or major IP delivery.
• RTL and microarchitecture experience in video, image processing, or ASIC datapaths.
• Understanding of ASIC design, verification, synthesis, timing, and power.
• Ability to learn unfamiliar topics quickly and ask clear, thoughtful questions.
• Ability to work independently and collaborate effectively across teams.
• Strong communication skills and a great team player.

Ways to stand out from the crowd

• Expertise in video codecs or video-processing standards.
• AI tool experience for design work, exploration, or result evaluation.
• Deep HLS knowledge: algorithm modeling, scheduling, RTL generation, and PPA tradeoffs.